Electronic design automation (EDA) software systems commonly perform generation of a clock tree that uses a branching network of fan-out buffers or fan-out inverters to distribute a clock signal from a root clock signal source to a set of clock sinks within a circuit design. The clock sinks can comprise devices in the circuit design to be clocked by a clock signal. A clock tree can vary in the number of buffers or inverters to fan-out and deliver a clock signal to clock sinks, and generally depends on the number of clock sinks that need to receive the clock signal.
After initially establishing positions of fan-out buffers or fan-out inverters and routing signal paths between them and clock sinks, a conventional clock tree synthesis (CTS) tool of an EDA software system can estimate the path delays from clock tree root to all clock sinks and then insert additional buffers or inverters into various branches of clock tree as needed to reduce variations in path delays to the clock sinks, thereby balancing the clock tree.